Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback

We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block the issuing of new instructions. The design has been optimized for low-power operation and has not been constrained by the formal verification effort. Additional improvements for the implementation were identified through formal verification. The formal verification of the design also incorporates the implementation of clock-gating and control logic. The core of the verification effort was based on ACL2 theorem proving. Additionally, model checking has been used to verify some properties of the floating-point scheduler that are relevant for the correct operation of the unit.Comment: In Proceedings ACL2 2011, arXiv:1110.447

On the Composition Problem for OBDDs With Multiple Variable Orders

Ordered Binary Decision Diagram (OBDD) is a favorite data structure used for representation Boolean functions in computer-aided synthesis and verification of digital systems. The secret of its success is the efficiency of the algorithms for Boolean operations, satisfiability and equivalence check. However, the algorithms work well under condition only that the variable order of considered OBDDs is the same. In this paper, we discuss the problem of Boolean operations on OBDDs with multiple variable orders, which naturally appears, e.g., in the connection with minimization techniques based on dynamic variable reordering. Our goal is to place the problem with respect to its complexity and to point out the difficulties in finding an acceptable solution

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A Unifying Theoretical Background for Some BDD-based Data Structures

In the paper, we propose a general concept (in what follows denoted by TBDD) for Boolean functions manipulation that is based on cube transformations. The basic idea is to manipulate a Boolean function by converting it by means of a cube transformation into a function that can be efficiently represented and manipulated in terms of ordered binary decision diagrams (OBDD's). We show that the new concept unifies and simplifies known BDD-based data structures considerably, and allows to work in all cases with the simple-structured and well--comprehended data struture of OBDD's (what is especially important from the point of practical applications.) Further, to give an example how TBDD's open new ways in the search for efficient data structures for Boolean functions, we discuss the data structure of typed kFBDD's

Accelerating OBDD-Minimization by Means of Structural and Semantical Properties

In many different applications in computer science, the representation of Boolean functions is done in terms of Ordered Binary Decision Diagrams (OBDD). This is particulary true in the field of computer aided design of VLSI circuits. Within the graph-based data structure of an OBDD the variable order may have a tremendeous impact on the size of the graph. An OBDD package is the core of diverse software systems for computer aided design and hence, its efficiency has a huge influence on the performance of these systems. Due to the impact of the chosen variable order on the OBDD-size as well memory as time requirements of such OBDD-packages depend strongly on how the problem of finding an optimal variable order is solved. Since this problem is known to be NP-hard, there is a need for efficient heuristics that find variable orderings in feasible time within an acceptable memory overhead. The most universal and successful approach for doing this is based on suited dynamical changes of the v..